1. Technical Field
The present invention relates generally to memory transfers and, more particularly, to memory controller optimization and a related method and program product for optimizing a memory controller.
2. Related Art
During arbitration on a memory bus, there is a significant amount of cycles that an internal memory controller spends waiting on an acknowledgement for an existing request from the memory bus. This lag time creates a number of disadvantageous situations. First, during the lag time, resources are underutilized because the memory bus and/or a corresponding memory controller are idle. Second, where a queue of pending memory requests is kept for the memory controller, higher priority pending requests may be forced to wait for completion of a lower priority existing request on the memory bus. In other situations, a pending request may have a higher priority than another pending request, but may not be positioned correctly in the queue. Current technology is known to adjust memory request priorities, i.e., re-arrange the queue, based on some selectable setting from an outside control. Unfortunately, any re-arrangement that does not actively re-prioritize pending requests based on bus activity is incapable of fully optimizing memory controller usage. In addition, current technology does not take advantage of efficiency that can be gained by aborting an existing request or interrupting an existing request to complete a pending request.
In view of the foregoing, there is a need in the art for a memory controller optimization by active re-prioritizing of pending requests based on memory bus activity and, where appropriate, aborting or interrupting an existing request.